What if you could design a cutting-edge semiconductor chip by describing what you want in plain English? Japan's new foundry Rapidus has built AI design tooling that does roughly that, and three companies are already using it. Here's what's inside it, and how far it sits from the rest of the field.

What Is Rapidus's "Raads" AI Design Agent?

On March 5, 2026, at the "RISC-V Day Tokyo 2026 Spring" conference in Tokyo, Rapidus director Hirokame Tsuruzaki reported on the state of the EDA (electronic design automation) system the company is building. At its center sits an AI-powered chip design tool suite called "Raads," which already has three active users: two Japanese companies and one overseas firm.

Raads stands for "Rapidus AI-Agentic Design Solution." It was originally "AI-Assisted"; the rebrand to "AI-Agentic" was announced at SEMICON Japan in December 2025. The stated goal is for Raads not merely to assist chip designers but to act as an AI agent in advanced semiconductor device design.

The notable part is that it's in use before the production line has ramped at all.

How the Raads Tool Suite Works

For readers unfamiliar with semiconductor jargon, designing a chip is an extraordinarily complex process. Engineers write code describing how millions (or billions) of tiny circuits should behave, then translate that into a physical layout that can be manufactured. This process can take months or years and cost tens of millions of dollars.

Raads aims to dramatically accelerate this with AI. Here's what each tool does:

Raads Generator uses a large language model (LLM), similar to the technology behind ChatGPT, to convert natural language chip specifications into RTL (Register Transfer Level) design code optimized for Rapidus's 2nm manufacturing process. Think of it as a semiconductor version of GitHub Copilot: describe what you want, and the AI writes the blueprint.

Raads Predictor solves one of chip design's biggest headaches. Feed it RTL design data along with Synopsys Design Constraints (SDC), and it estimates the power, performance, and area (collectively "PPA") of the chip as Rapidus would fabricate it. Normally those numbers only firm up late in the process, and bad ones mean going back and redesigning.

Raads SynthCast integrates Generator and Predictor into one. These three are the tools Rapidus developed itself, all for upstream design.

Additional tools rolling out from fiscal 2026 include Raads Navigator/Indicator (an LLM-powered design QA assistant), Raads Manager (machine-learning hierarchical layout design), and Raads Optimizer (ML-driven PPA parameter search).

Rapidus claims that using Raads alongside conventional EDA tools can cut design time by 50% and reduce design costs by 30%.

Why Is a Chip Factory Building AI Software?

Design tools are normally the province of specialists like Synopsys, Cadence, and Siemens EDA, not the factories that physically produce chips. Rapidus isn't trying to replace all of that.

Raads splits into two kinds. One takes EDA vendors' AI-capable tools and layers Rapidus's trained models for its 2nm process on top; that's what's used converting RTL into GDS-II mask layout data. The other is the three upstream tools above, which Rapidus built itself. Keeping vendor products at the core is a pragmatic call about development effort and about how hard it is to get designers to switch flows.

The differentiation lives in the trained models. Under Rapidus's "RUMS" (Rapid and Unified Manufacturing Service) model, the IIM-1 factory in Chitose, Hokkaido processes wafers one at a time rather than in batches, across every process step. That yields granular manufacturing data for each individual wafer, which feeds back into the AI models. Engineers call the result DMCO, Design-Manufacturing Co-Optimization: what you learn from making chips improves how you design them.

Raads is less a standalone design tool than a pipeline of models tied to Rapidus's own process.

How Does Raads Compare to TSMC and Intel's AI Efforts?

Every major player in semiconductors is now deploying AI in chip design. Here's how they stack up:

TSMC collaborates with all three major EDA vendors (Synopsys, Cadence, Siemens) through its Open Innovation Platform, and has validated AI-driven design flows for its N2 (2nm) node. It relies on external EDA partners rather than building its own AI tools in-house, which is, notably, not so far from Rapidus's own vendor-centric structure.

Intel has researched machine learning for chip design and concluded AI alone isn't sufficient, arguing that classical search methods combined with ML do better than pure AI approaches. Intel also collaborates with Synopsys on certified design flows for its 18A process.

NVIDIA, better known for GPUs, runs an EDA research team developing AI methods including Bayesian optimization and reinforcement learning for chip design problems, with Best Paper recognition at conferences like DAC 2025.

Synopsys, The EDA giant introduced its "Synopsys.ai Copilot" in 2023, which automates RTL generation and testbench creation. Collaborations with AMD, Intel, and Microsoft have demonstrated 5-10x reductions in verification time.

What sets Raads apart is the direct feedback loop with manufacturing data. Others optimize generically; Raads carries models tuned to Rapidus's 2nm process, so the designs come out pre-fitted to that line. The flip side is that the value only lands for customers who have already chosen to build there.

Rapidus's Road to 2nm Mass Production

Understanding Raads requires knowing where Rapidus stands as a company. Here's the timeline:

ASML delivered an EUV lithography system in December 2024, and in April 2025 Rapidus achieved EUV exposure at the IIM-1 facility in Chitose, Hokkaido. On July 18, 2025, it announced that it had prototyped 2nm GAA (Gate-All-Around) transistors and confirmed they worked. Early characteristics weren't where the company wanted them, but the improvement curve since September has been steep: work that took a year and a half at IBM's Albany site reportedly took under two months at Chitose.

On February 27, 2026, Japan's Ministry of Economy, Trade and Industry announced a combined public-private investment of ¥267.6 billion (roughly $1.7 billion): ¥100 billion from the government via the IPA, and ¥167.6 billion from 32 private companies including Canon, Fujitsu, NTT, SoftBank, Sony Group, and Toyota. That private figure beat the ¥130 billion the government had projected in November 2025. The state became the largest shareholder with 11.5% of voting rights and holds a golden share with veto power over key decisions. Counting R&D commissioning funds alongside equity, cumulative government support is planned to reach roughly ¥2.9 trillion ($19 billion) through fiscal 2027.

The roadmap targets mass production in the second half of fiscal 2027, starting at 6,000 wafers per month and reaching 25,000 within a year, then advancing to 1.4nm and 1.0nm every two to three years. Specific dates like 1.4nm production in 2029 or an IPO in fiscal 2031 have been reported, but Rapidus has not announced them officially.

Where Raads Fits in Japan's Semiconductor Revival

Japan once commanded over 50% of the global semiconductor market. By the early 2020s, that share had dropped below 10%, with virtually zero domestic manufacturing capacity for cutting-edge logic chips. Rapidus represents the centerpiece of Japan's national project to reverse this decline.

Critically, Rapidus isn't trying to beat TSMC at its own game of massive-scale production. Instead, it targets a niche: fast turnaround, low-volume, high-mix manufacturing. Where TSMC produces tens of thousands of wafers per month for mass-market clients like Apple and NVIDIA, Rapidus aims to serve companies that need cutting-edge chips quickly in smaller quantities, think AI startups, autonomous driving developers, and specialized computing firms.

Raads is a linchpin of that strategy. Designs that arrive pre-fitted to the Rapidus process mean fewer manufacturing iterations and faster turnaround. Partnerships with Preferred Networks and Sakura Internet on data center chips point the same direction. What's missing is the part that matters most: no volume production record, no yield data. Who actually buys from Rapidus is still an open question.

The foundry race is shifting from manufacturing technology alone toward the depth of the design ecosystem around it. 2026 is the year designers using Raads decide whether it's good enough.

In Japan, opinions are split between excitement over this AI-first approach and skepticism about whether it can truly compete. How is AI being used in semiconductor design in your country? What do you think about national semiconductor revival projects, are they worth the investment?

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