🔬 To make the most advanced semiconductors, the "master template" must be flawless. Circuit lines just 2nm wide — about 50,000 times thinner than a human hair — demand perfection at the atomic scale. And in this invisible battle, a Japanese printing company is leading the charge. DNP (Dai Nippon Printing) has invested in Rapidus to mass-produce EUV photomasks — the "original plates" of the chip world.
DNP Invests in Rapidus — What's the Strategy?
On February 27, 2026, Dai Nippon Printing Co., Ltd. (DNP) announced an investment in Rapidus Corporation. The purpose is clear: to support the development of wafer manufacturing processes using EUV (Extreme Ultraviolet) lithography for next-generation semiconductors.
DNP is best known as a printing company, but its ultra-precision printing expertise has become a critical asset in photomask manufacturing — one of the most demanding components in chipmaking. A photomask functions like a photographic negative: it carries the circuit pattern that gets projected onto silicon wafers to create semiconductor chips. The finer the circuits become, the more exacting the photomask must be.
Rapidus aims to mass-produce 2nm-generation logic semiconductors by 2027 at its factory in Chitose, Hokkaido. The key component enabling that goal? The EUV photomask — and that's exactly what DNP is building.
EUV Lithography and Photomasks — Why They're a Bottleneck
The process of transferring circuit patterns onto wafers is called lithography. Traditionally, DUV (Deep Ultraviolet) light sources handled this task. But when circuit widths shrank below 7nm, the industry needed shorter-wavelength light — enter EUV lithography, operating at just 13.5nm wavelength.
Here's what makes EUV fundamentally different: instead of light passing through the photomask, it reflects off it. This requires a completely different mask structure — a multilayer reflective coating made of 40 to 50 alternating layers of silicon and molybdenum. Even the tiniest defect or dimensional variation in this structure can tank chip yields, which is why EUV photomasks are often called the bottleneck of advanced semiconductor manufacturing.
At the 2nm node, pattern sizes shrink more than 20% compared to 3nm, and manufacturers must resolve not just straight lines and rectangles but complex curved patterns on a single mask. DNP completed its 3nm manufacturing process in 2023 and has already demonstrated the ability to resolve patterns for 2nm and beyond.
The NEDO Project and DNP's Role
In 2024, DNP was selected as a subcontractor within a major national research initiative. Rapidus participates in NEDO's (New Energy and Industrial Technology Development Organization) "Research and Development Project of the Enhanced Infrastructures for Post-5G Information and Communication Systems." DNP joined as a subcontractor to develop EUV photomask manufacturing processes and quality assurance technology for cutting-edge logic semiconductors.
To support this work, DNP expanded its fleet of multi-beam mask writing tools to three units by the end of fiscal 2024. These machines fire over 200,000 electron beams simultaneously to write the complex mask patterns required for EUV exposure at high speed. Notably, DNP was the first merchant photomask manufacturer in the world to deploy this type of equipment back in 2016.
The roadmap: complete 2nm photomask process development by the end of fiscal 2025, shift to production technology and yield improvement from fiscal 2026, and begin supplying mass-production photomasks to Rapidus's Chitose factory in fiscal 2027. DNP has set a revenue target of approximately $65 million for its EUV photomask business by fiscal 2030.
Looking Beyond 2nm — The Path to 1.4nm and High-NA EUV
DNP's ambitions extend well past the 2nm generation. The company has signed a joint development agreement with imec, the Belgium-based international semiconductor research organization, to co-develop next-generation EUV photomasks.
For 1.4nm and beyond, the industry is preparing for "High-NA EUV lithography" — next-generation exposure systems being developed by ASML with a numerical aperture of 0.55, compared to the current 0.33 NA tools. While High-NA enables even finer patterning, it demands photomasks built with entirely different process flows. DNP has already completed basic evaluation of High-NA compatible photomasks and begun supplying evaluation samples to semiconductor development consortia and equipment manufacturers.
Japan's Dominant Position in the Global Photomask Landscape
In the photomask industry, Japanese companies hold extraordinary influence. In the merchant market — sales to chipmakers, excluding in-house production — Techsend Photomask (formerly Toppan Photomask, a TOPPAN Holdings subsidiary) leads the world with roughly 39% share, followed by Photronics of the U.S., with DNP in third. The top three account for well over 90% of the market — a concentrated field led by Japanese players.
Each player occupies a distinct strategic position:
Techsend Photomask (a TOPPAN Holdings subsidiary, renamed from Toppan Photomask in November 2024) is the world leader in merchant photomasks. In February 2024, it began joint development with IBM on photomasks for the 2nm logic node, including High-NA EUV.
HOYA holds an even more strategically critical position — not in finished photomasks, but in mask blanks, the base substrates from which photomasks are made. Mask blanks are a concentrated market: Japan's HOYA, Shin-Etsu Chemical, and AGC together hold roughly 90% of the world share, with HOYA holding a strong position in EUV mask blanks in particular. It is among the few vendors with validated products for High-NA EUV systems, making it hard to replace in the advanced semiconductor supply chain.
Think of it this way: HOYA provides the "canvas" (the blank substrate), while DNP and TOPPAN paint the "picture" (the circuit patterns) on it. The fact that Japan covers the entire EUV photomask supply chain — from raw substrates to finished masks — carries enormous significance in semiconductor geopolitics.
The Geographic Advantage of Domestic Partnership
A key advantage DNP emphasizes in its Rapidus collaboration is proximity. With Rapidus's fab located domestically in Chitose, Hokkaido, the cycle from photomask prototyping to evaluation, feedback, and improvement can be compressed dramatically. Where international logistics and export controls might add weeks to this process for overseas foundries, domestic turnaround can be measured in days.
Rapidus's timeline — founded in 2022 with mass production targeted for 2027 — is exceptionally aggressive by semiconductor industry standards. Achieving this requires supply chain proximity, and for DNP, having a cutting-edge customer next door accelerates its own technical improvements.
While Rapidus is DNP's primary customer, the company has its sights set on future orders from major overseas foundries including TSMC, positioning Japan as a global hub for EUV photomask supply.
The Big Picture — A "Printing Nation" Powering the Semiconductor Future
Japan's semiconductor comeback isn't just about building cutting-edge chip factories. Behind the scenes, companies specializing in photomasks — the invisible "master templates" — are supporting global chip manufacturing from the ground up. DNP's investment in Rapidus isn't simply a financial bet; it's a strategic partnership that directly connects Japan's photomask technology with next-generation chip production.
In Japan, many people are surprised to learn that printing technology shapes the future of semiconductors. Others remain skeptical about whether Rapidus can truly achieve mass production by 2027. What about in your country — how are the materials and components needed for semiconductor manufacturing being developed? We'd love to hear your perspective.
References
- https://prtimes.jp/main/html/rd/p/000000970.000069194.html
- https://www.global.dnp/news/detail/20173706_4126.html
- https://optronics-media.com/news/20241213/96415/
- https://eetimes.itmedia.co.jp/ee/articles/2412/13/news103.html
- https://www.nikkei.com/compass/industry_s/0252
- https://karimalmansour.substack.com/p/on-mask-blanks-and-the-substrate
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